The present invention relates to a data processor capable of processing instructions at a high speed.
The data processor of the prior art comprises, as shown in FIG. 1, an interface circuit 7 for data transfer with a main memory 5, an instruction control unit 3 for controlling an instruction to be executed, and an instruction execution unit 4 for executing the instruction. When an instruction read out from the main memory 5 is transferred to an instruction control unit 3 via a line 73, the interface circuit 7 and a line 11, the instruction control unit 3 analyzes the instruction and transfers the result to the instruction execution unit 4 over a line 15. (It will be recognized that lines 73, 11 and 15 along with others to be described herein include more than one wire and are actually buses. Thus, the use of the term "line" herein includes both single conductors and multiple conductors.) As a result of the analysis, the instruction execution unit 4 generates a variety of control signals so that respective gates in the instruction execution unit 4 are opened or closed by those control signals to execute processing such as arithmetic operation, storage or shift. An instruction designates an address via lines 14 and 74 to read out data from the main memory 5 via line 13 and 73 or write the arithmetic result in the main memory 5. The instruction control unit 3 designates the read address of a subsequent instruction in the main memory 5 via a line 12, the interface circuit 7 and the line 74. By repeating a series of those operations, data processor 1 executes the program which is stored in the main memory 5.
This processor of the prior art is equipped with a cache memory 71 to allow reading data from the main memory 5 at high speed. The cache memory 71 is addressed by the address on line 74 so that the data in the corresponding entry are read out but the main memory 5 is not accessed when the cache memory 71 is accessed. Consequently, when data are read out from the cache memory, accessing the main memory is unnecessary, so that reading out of data is much faster than it would be without said cache memory.
This processor is exemplified by the data processor which is disclosed on pages 144 to 148 of the Iwanami Microelectronics Course, Vol. 5, "Microcomputer Hardare", November, 1994.
In this processor, however, both the instruction control unit 3 and the instruction execution unit 4 use lines 73 and 74, and the cache memory 71 jointly when pipeline control is to be effected. To prevent conflict, therefore, a selector 72 may inhibit concurrent use so that one of the units is held on standby.